NET "extCLK_50M" PERIOD = 20 ns HIGH 50%; 


##NET "CLK_50M" LOC = "T9" | IOSTANDARD = LVCMOS33;
NET "extCLK_50M" LOC = "T9" |IOSTANDARD = LVTTL;

##NET "PS2_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
##NET "PS2_DATA" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
NET "PS2_CLK" LOC = "T7" |IOSTANDARD = PCI33_3;
NET "PS2_DATA" LOC = "T8" |IOSTANDARD = PCI33_3;


##NET "LINE_IN" LOC = "T6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "LINE_IN" LOC = "T6" |IOSTANDARD = LVTTL;

NET "LATCH_D0" LOC = "T12" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;
NET "LATCH_D4" LOC = "T10" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;

NET "VIDEO_DATA" LOC = "P1" |IOSTANDARD = LVTTL;
NET "VIDEO_SYNC" LOC = "N1" |IOSTANDARD = LVTTL;

NET "VGA_HSYNC" LOC = "A10" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;
NET "VGA_VSYNC" LOC = "A9" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;
NET "VGA_R" LOC = "A6" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;
NET "VGA_G" LOC = "A8" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;
NET "VGA_B" LOC = "A7" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST;

NET "DQext<0>" LOC = "C1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<1>" LOC = "D1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<2>" LOC = "E1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<3>" LOC = "F1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<4>" LOC = "G1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<5>" LOC = "H1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<6>" LOC = "J1" | IOSTANDARD = LVTTL | PULLUP;
NET "DQext<7>" LOC = "K1" | IOSTANDARD = LVTTL | PULLUP;

NET "RDnext" LOC = "L1" | IOSTANDARD = LVTTL | PULLUP;
NET "WRnext" LOC = "M1" | IOSTANDARD = LVTTL | PULLUP;

NET "Aext<0>" LOC = "C16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<1>" LOC = "D16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<2>" LOC = "E16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<3>" LOC = "F16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<4>" LOC = "G16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<5>" LOC = "H16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<6>" LOC = "J16" | IOSTANDARD = LVTTL | PULLUP;
NET "Aext<7>" LOC = "K16" | IOSTANDARD = LVTTL | PULLUP;

NET "M1next" LOC = "L16" | IOSTANDARD = LVTTL | PULLUP;
NET "IORQnext" LOC = "M16" | IOSTANDARD = LVTTL | PULLUP;




NET "/PBLAZE_VWR_VGA" TIG;
NET "/PBLAZE_VADDR_VGA<0>" TIG;
NET "/PBLAZE_VADDR_VGA<1>" TIG;
NET "/PBLAZE_VADDR_VGA<2>" TIG;
NET "/PBLAZE_VADDR_VGA<3>" TIG;
NET "/PBLAZE_VADDR_VGA<4>" TIG;
NET "/PBLAZE_VADDR_VGA<5>" TIG;
NET "/PBLAZE_VADDR_VGA<6>" TIG;
NET "/PBLAZE_VADDR_VGA<7>" TIG;
NET "/PBLAZE_VADDR_VGA<8>" TIG;
NET "/PBLAZE_VADDR_VGA<9>" TIG;
NET "/PBLAZE_VADDR_VGA<10>" TIG;
NET "/PBLAZE_VADDR_VGA<11>" TIG;
NET "/PBLAZE_VADDR_VGA<12>" TIG;
NET "/PBLAZE_VADDR_VGA<13>" TIG;
NET "/PBLAZE_VADDR_VGA<14>" TIG;
NET "/PBLAZE_VADDR_VGA<15>" TIG;

NET "/PBLAZE_VDATA_VGA" TIG;

NET "/iPIX_CLK" PERIOD = 20 ns HIGH 50%; 
NET "/CLK_50M_VGA" PERIOD = 20 ns HIGH 50%; 

NET "/PDIV(0)" PERIOD = 40 ns HIGH 50%;
##NET "/CPU_CLK_n" PERIOD = 40 ns HIGH 50%;
NET "/VGAOUT/CLK_25M" PERIOD = 40 ns HIGH 50%;
NET "/pblaze_soc/dna_clk" PERIOD = 100 ns HIGH 50%;
NET "/pblaze_soc/sck" PERIOD = 100 ns HIGH 50%;